On the modern FPGA device Virtex-7, a basic iterative architecture of ICEPOLE reaches around 40 Gbits/s, which is over 10 times faster than the equivalent implementation of AES-128-GCM. The throughput-to-area ratio is also substantially better when compared to AES-128-GCM.

Detailed numbers and preliminary comparison with other authenticated ciphers can be found at ATHENa database.


Cyril Arnould from ETHZ, Zurich implemented ICEPOLE in ASIC (tape-out included!). It was part of his Master’s Thesis "Towards Developing ASIC and FPGA Architectures of High-Throughput CAESAR Candidates", supervised by Michael Muehlberghuber and Frank K. Gürkaynak. Some of their findings were presented at DIAC 2015 Conference. Highlights are:

Software Implementation

While the primary focus of the ICEPOLE design is hardware performance, the cipher is also amenable to efficient software implementations. We measured that our rather straightforward C implementation compiled for speed (with no beyond-C optimization efforts like code vectorization using AVX or intrinsics use) runs for very long messages at about 9 cycles per byte on Intel Ivy Bridge i5-3320M processor. The same implementation runs at about 8 cycles per byte on a Haswell (Intel Xeon E3 1275) machine.