ICEPOLE is a high-speed, hardware-oriented authenticated cipher, suitable for high-throughput network nodes or generally any environment, where specialized hardware (such as FPGAs or ASICs) can be used to provide high data processing rates. ICEPOLE-128 (the primary ICEPOLE variant) is very fast. On the modern FPGA device Virtex-7, a basic iterative architecture of ICEPOLE reaches around 40 Gbits/s, which is over 10 times faster than the equivalent implementation of AES-128-GCM. The throughput-to-area ratio is also substantially better when compared to AES-128-GCM.
We have carefully examined the security of the algorithm through a range of cryptanalytic techniques and our findings indicate that ICEPOLE is a secure algorithm. The third-party analysis also supports this claim.
ICEPOLE was submitted to the CAESAR competition and presented at CHES'14 Conference. The project is financed by National Science Centre, Poland, project registration number UMO-2014/15/B/ST6/05130.
- Paweł Morawiecki (Polish Academy of Sciences, Institute of Computer Science)
- Kris Gaj (Cryptographic Engineering Research Group, George Mason University, USA)
- Ekawat Homsirikamol (Cryptographic Engineering Research Group, George Mason University, USA)
- Krystian Matusiewicz (Intel, Gdańsk, Poland)
- Josef Pieprzyk (QUT, Brisbane, Australia and Polish Academy of Sciences, Institute of Computer Science)
- Marcin Rogawski (Cadence Design Systems, San Jose, USA)
- Marian Srebrny (Polish Academy of Sciences, Institute of Computer Science)
- Marcin Wójcik (Cryptography and Information Security Group, University of Bristol, United Kingdom)